Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration

Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to creation dense synaptic connections for bio-inspired neuromorphic circuits. One drawback OxRAM based systems is relatively low ON resistance synapses (in range just a few kilo-ohms). This requires large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability power operation. After learning, however, read inference can be made low-power by applying very small amplitude pulses, which require much smaller synapse. Here we propose experimentally demonstrate technique reduce pulses in monolithic CMOS OxRAM-synaptic crossbar systems. Unfortunately, tiny non-trivial due presence random DC offset voltages. To overcome this, finely calibrating voltages using bulk-based three-stage on-chip calibration technique. In this work, spiking pattern recognition STDP learning 4×4 proof-of-concept memristive crossbar, where implemented pulse could as 2mV. A chip pre-synaptic calibrated input neuron drivers 1T1R synapse was designed fabricated CEA-LETI MAD200 technology, uses OxRAMs above ST130nm CMOS. Custom-made PCBs hosting post-synaptic circuits control FPGAs were used test different experiments, including characterization, template matching, use offset-calibrated amplifiers. According our minimum possible limited voltage drifts noise. We conclude paper some suggestions future work direction.